BabyWR is being developed as a cost effective and small pluggable WR node. BabyWR has a M.2 form-factor. BabyWR is designed for low phase noise (10 MHz; < -100 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
The standard M.2 Type 2260-D6-M form factor module provides 10 MHz and 1 PPS signals that are generated by the White Rabbit PTP Core.

FPGA phase noise is the limiting factor. Phase noise can be further improved when re-clocking the 10 MHz and 1 PPS signals using the clean reference oscillator as is proven for the M.2 Type 2280-D6-M form factor module. However, for re-clocking “lock sweep” “GTHE4 RXOUTCLKPMA jumps 1.6 ns with respect to input serial bit stream due to FPGA die temperature” needs to be implemented in order to find the proper phase alignment. Lock sweep increases the time it takes to establish a link and lock sweep is not yet officially implemented; two reasons to use standard M.2 Type 2260-D6-M for the time being.

BabyWR-Carrier is a SPEC like PCIe card (Figure 3) that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP+ cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface, LEDs, button and GPIO headers.

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